Five forces converging on the wafer

For most of the last decade, quantum processors were built in small batches on lab-scale tooling. That changed in late 2025. IBM announced it had doubled the speed of its chip development cycle, shifted primary fabrication of its quantum processors to a 300mm wafer facility at the Albany NanoTech Complex, and increased the physical complexity of its chips roughly tenfold in support of its fault-tolerance roadmap. The company's Nighthawk processor (120 qubits, square-lattice topology) and Loon chip (demonstrating the hardware building blocks for error correction) are the first products of that shift, with IBM targeting community-verified quantum advantage by the end of 2026 and large-scale fault-tolerant computing by 2029.

IBM is not alone. Google has deepened its collaboration with Nvidia on CUDA-Q for large-scale physical simulation of next-generation processors and opened cloud access to its Willow chip for research partners. Microsoft's Majorana 1, unveiled in February 2025, moved the company's topological qubit research from theory to a hardware prototype. Quantum-hardware directories now track more than 200 companies globally, spanning superconducting, trapped-ion, neutral-atom, and photonic approaches — several of which, like PsiQuantum, are explicitly building dedicated wafer-scale fabrication capacity (a 300mm line at GlobalFoundries Fab 8, and new "Kilofab"-class facilities designed to industrialize quantum chip output).

Wafer-scale integration is also reshaping classical AI infrastructure. Cerebras builds its Wafer Scale Engine from a nearly whole 12-inch silicon wafer rather than dicing it into individual GPU dies — its third generation carries roughly 4 trillion transistors and 900,000 AI-optimized cores, and the company describes the resulting chip as many times larger than a leading-edge GPU. By keeping compute, on-chip memory, and interconnect on one substrate, the architecture removes the die-to-die communication bottleneck that forces conventional GPU clusters to rely on external interconnects such as NVLink.

The commercial case strengthened materially in 2026. Cerebras completed one of the year's largest Nasdaq listings, and has lined up multi-hundred-megawatt data-center commitments with major AI labs and cloud providers for inference workloads specifically. It is not the only entrant: a widening set of accelerator and neocloud vendors are pursuing similar "more silicon, fewer boundaries" strategies as training and inference workloads scale past what standard multi-GPU racks can efficiently serve.

On June 22, 2026, President Trump signed two executive orders that reset the federal posture on quantum technology. "Ushering in the Next Frontier of Quantum Innovation" establishes a national effort — the Quantum Computer for Application Development and Discovery Science (QC-ADDS) program — to deliver a scientifically useful quantum computer to a Department of Energy facility, directs agencies to strengthen the domestic quantum supply chain and foundry access, and instructs Commerce and Energy to explore advance market commitments and private-sector partnerships. A companion order, "Securing the Nation Against Advanced Cryptographic Attacks," compresses the federal government's post-quantum cryptography migration timeline to 2030 (key establishment) and 2031 (digital signatures) — years ahead of the prior 2035 target.

These orders followed the Department of Commerce's move to take roughly $2 billion in equity stakes across nine leading U.S. quantum companies, and build on the administration's earlier Genesis Mission executive order applying AI to accelerate scientific discovery, including in quantum research. Officials framed quantum, AI, and advanced semiconductors as a unified "three-part foundation" for the next era of computing — language that sits precisely at the intersection this domain occupies.

Chinese quantum and semiconductor programs are pursuing wafer-scale fabrication capacity on a parallel track, with domestic directories now tracking a distinct ecosystem of Chinese quantum computing companies alongside the Western vendors profiled above. The 2026 discourse in Chinese industry press has framed this as a race to displace GPU-centric compute with quantum processing units, alongside continued state investment in domestic advanced packaging and wafer fabrication to reduce dependence on Western foundries. For a neutral, dual-market domain, this bifurcated competitive landscape widens the buyer pool rather than narrowing it — both blocs need Western-facing brand assets for investor communication and enterprise sales.

"Neocloud" operators — infrastructure-focused providers built specifically to sell GPU and accelerator capacity rather than general-purpose cloud — have emerged as the commercial layer sitting directly on top of this hardware shift. Their core pitch is aggregation: pooling GPUs, CPUs, and increasingly specialized accelerators into unified fabric that can be sold as training or inference capacity. That capacity increasingly serves not just large language models but physical AI (robotics, autonomous systems) and AI agent workloads that require sustained, low-latency inference at scale. A domain that names the physical substrate underneath all of it — the wafer — sits above any single vendor's product name and below the generic "AI infrastructure" category, occupying a naming layer that has not yet been claimed.